1. Field of the Invention
The present invention relates to a level conversion circuit for converting an input pulse to a high-voltage or low-voltage pulse according to the level of operating voltage of a logical circuit connected in a subsequent stage, and an input-output device using the level conversion circuit.
2. Description of the Related Art
FIG. 9 shows an existing voltage raising type level conversion circuit 400. While this level conversion circuit 400 is used commonly and widely, the level conversion circuit 400 causes indeterminate operation at a starting time of power supply voltage. In addition, because high breakdown voltage MOS (Metal Oxide Semiconductor) transistors HMN1 (401), HMN2 (402), HMP1 (403), and HMP2 (404) are used as shown in FIG. 9, the level conversion circuit 400 may not be operated with a power supply voltage lower than the threshold value of a high breakdown voltage N (N-channel) MOS transistor.
As means for solving the former problem, a level conversion circuit 450 shown in FIG. 10, for example, is disclosed in Japanese Patent Laid-Open No. 2005-323195 referred to as Patent Document 1 hereinafter. In this method, however, a latch circuit formed by an inverter 453 and a NAND circuit 454 is operated by a power-on reset signal (POR). Thus, an initial value can be determined, and the problem of a power supply sequence is remedied. However, because the circuit is formed by high breakdown voltage MOS transistors alone, operation with low power supply voltage may not be performed. In addition, the latter problem still remains. Further, because high breakdown voltage MOS transistors generally have a slow operating speed, higher speed may not be achieved easily.
As means for solving the latter problem, a level conversion circuit 500 shown in FIG. 11, for example, is disclosed in Japanese Patent Laid-Open No. 2005-311712 referred to as Patent Document 2 hereinafter. This method enables power supply voltage to be lowered, but is not ready for a free power supply sequence. In addition, because the level conversion circuit (500) itself does not have a circuit for setting an initial value, a value at a starting time is undetermined. Further, because bias (BIAS) voltage starts quickly, in a case where a low voltage power supply VDDL starts slowly after a high voltage power supply VDDH starts, the level conversion circuit operates while an input signal remains undetermined, so that erroneous operation occurs.
FIG. 12 shows a voltage lowering type level conversion circuit. As shown in FIG. 12, in this circuit, inverters are formed simply by high breakdown voltage MOS transistors, and therefore operation may not be performed with a low power supply voltage VDDL lower than the threshold value of the high breakdown voltage MOS transistors. As means for solving this problem, a voltage lowering type level conversion circuit 600 as shown in FIG. 13, for example, is disclosed in Japanese Patent Laid-Open No. 2005-64952 referred to as Patent Document 3 hereinafter. This method makes it possible to lower the voltage of the low voltage power supply VDDL, but has a disadvantage of consumption of a DC current because voltage division is performed by resistances R1 (603) and R2 (604) as shown in FIG. 13 or a diode connection of a MOS transistor not shown in the figure. In addition, when the resistance values of the resistances R1 (603) and R2 (604) are increased and the DC current is decreased, operating speed becomes slow.
As another existing technique, a level conversion circuit 650 shown in FIG. 14 is disclosed in Japanese Patent Laid-Open No. 2005-333595 referred to as Patent Document 4 hereinafter. In the circuit of FIG. 14, a PMOS transistor side is changed to low breakdown voltage MOS transistors LMP1 (652) and LMP2 (653), so that operation can be performed with a low power supply voltage VDDL lower than the threshold value of a high breakdown voltage MOS transistor. However, because the cross-coupled PMOS transistors LMP1 (652) and LMP2 (653) are inverted, there is a problem of an increase in current in a transient state, and there is a disadvantage of provision being not made for a free power supply sequence.